Memory string and semiconductor device including the same

ABSTRACT

A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to k th  memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘ 2’.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent applicationnumber 10-2013-0132088 filed on Nov. 1, 2013, in the Korean IntellectualProperty Office, the entire disclosure of which is incorporated byreference herein.

BACKGROUND

1. Technical Field

Various embodiments of the present invention relate to electronicdevices. More specifically, the exemplary embodiments of the presentinvention relate to memory strings and a semiconductor device includingthe same.

2. Related Art

A non-volatile memory device is a memory device capable of retainingdata stored therein even when power cut-off occurs, and it may includememory strings as a cell array for storing data. Here, each of thememory strings includes a drain selection transistor, a plurality ofmemory cells, and a source selection transistor that are connected inseries. Each of the memory strings is connected to a source line via thesource selection transistor, and connected to a bit line via the drainselection transistor.

The memory strings are arranged on a substrate in a horizontal orvertical direction. In the related art, memory strings are arranged on asubstrate in the horizontal direction by forming memory cells in asingle layer. However, a method of arranging memory strings on asubstrate in the vertical direction by stacking memory cells has beensuggested.

However, memory strings having the structure described above are limitedin increasing cell current. Furthermore, when memory strings arearranged in the vertical direction, the properties of a memory devicemay be degraded due to interferences between memory cells adjacent inx/y/z-axis direction, respectively.

BRIEF SUMMARY

One or more exemplary embodiments of the present invention are directedto memory strings having improved properties and a semiconductor deviceincluding the same.

One aspect of the present invention provides a memory string including apass transistor, first memory cells connected in series to a drainterminal of the pass transistor, and first to k^(th) memory cell groupsconnected in parallel to a source terminal of the pass transistor andeach including a plurality of second memory cells connected in series,wherein k denotes an integer that is equal to or greater than ‘2’.

Another aspect of the present invention provides a semiconductor deviceincluding first and second memory strings each including a passtransistor, drain-side memory cells connected in series to a drainterminal of the pass transistor, and first and second source-side memorygroups connected in parallel to a source terminal of the pass transistorand each including a plurality of source-side memory cells connected inseries.

Further aspect of the present invention provides a semiconductor deviceincluding a first channel layer including a first pipe channel layer,and a first source-side channel layer, a first drain-side channel layer,and a second source-side channel layer connected to the first pipechannel layer and arranged in a first direction, first source-side gatesstacked and surrounding the first source-side channel layer, secondsource-side gates stacked and surrounding the second source-side channellayer, and first drain-side gates stacked and surrounding the firstdrain-side channel layer, wherein the first source-side gates, thesecond source-side gates, and the first drain-side gates are separatedfrom one another.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings in which:

FIG. 1A is a circuit diagram of a memory string according to anexemplary embodiment of the present invention;

FIGS. 1B and 1C are circuit diagrams illustrating memory stringsaccording to exemplary embodiments of the present invention;

FIGS. 2A and 2B are circuit diagrams illustrating program operationsperformed on the memory string according to the exemplary embodiment ofthe present invention;

FIGS. 3A and 3B are circuit diagrams illustrating read operationsperformed on the memory string according to the exemplary embodiment ofthe present invention;

FIGS. 4A to 4C are cross-sectional views of semiconductor devicesincluding memory strings according to exemplary embodiments of thepresent invention;

FIG. 5 is a block diagram of a memory system according to an exemplaryembodiment of the present invention;

FIG. 6 is a block diagram of a memory system according to anotherexemplary embodiment of the present invention;

FIG. 7 is a block diagram of a computing system according to anexemplary embodiment of the present invention; and

FIG. 8 is a block diagram of a computing system according to anotherexemplary embodiment of the present invention.

DETAILED DESCRIPTION

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. In the drawings, the thicknesses of anddistances between elements may be exaggerated for clarity. In thepresent disclosure, well-known functions or constructions that are notrelated to the gist of the present invention may not be described. Whenreference numerals are assigned to the elements shown in the drawings,the same reference numeral is assigned to the same elements even ifthese elements are illustrated in different drawings.

FIG. 1A is a circuit diagram of a memory string according to anexemplary embodiment of the present invention.

Referring to FIG. 1A, the memory string according to an exemplaryembodiment of the present invention includes at least one passtransistor PTr, a plurality of first memory cells connected in series toa drain terminal of the pass transistor PTr, and first to k^(th) memorycell groups connected in parallel to a source terminal of the passtransistor PTr. Here, each of the memory cell groups includes aplurality of second memory cells connected in series. In addition, thefirst memory cells may be drain-side memory transistors D_MT, and thesecond memory cells may be source-side memory transistors S_MT1 toS_MTk. Here, ‘k’ denotes an integer that is equal to or greater than‘2’.

The drain-side memory transistors D_MT are connected in series to adrain terminal of the at least one pass transistor PTr. The first tok^(th) source-side memory transistors S_MT1 to S_MTk are connected inparallel to a source terminal of the at least one pass transistor PTr.

The memory string according to an exemplary embodiment of the presentinvention further includes a drain selection transistor DST, and firstto k^(th) source selection transistors SST1 to SSTk. For example, atleast one drain selection transistor DST is connected in series to thedrain-side memory transistors D_MT, at least a first source selectiontransistor SST1 is connected in series to the first source-side memorytransistors S_MT1, and at least a k^(th) source selection transistorSSTk is connected in series to the k^(th) source-side memory transistorsS_MTk.

Here, the drain selection transistor DST is connected to a bit line BL,the first source selection transistor SST1 is connected to a firstsource line SL1, and the second source selection transistor SST2 isconnected to a second source line SL2.

In the structure described above, one memory string is connected to onebit line BL and a plurality of source lines SL1 to SLk. Thus, the firstto k^(th) source-side memory transistors S_MT1 to S_MTk are driven bydifferent source lines SL1 to SLk, respectively. For example, the firstsource-side memory transistors S_MT1 are driven by the first source lineSL1, and the k^(th) source-side memory transistors S_MTk are driven bythe k^(th) source line SLk. As described above, the amount of cellcurrent may be increased by connecting the plurality of source lines SL1to SLk to one memory string.

FIGS. 1B and 1C are circuit diagrams illustrating memory stringsaccording to exemplary embodiments of the present invention.

Referring to FIG. 1B, a first memory string and a second memory stringaccording to an exemplary embodiment of the present invention may bedriven by different bit lines BL1 and BL2 and different source linesS11, S12, S21, and S22.

In the first memory string, first source-side memory transistors S_MT11are driven by the first source line SL11 and second source-side memorytransistors S_MT12 are driven by the second source line SL12. The firstmemory string is driven by the first bit line BL1.

In the second memory string, third source-side memory transistors S_MT21are driven by the third source line SL21, and fourth source-side memorytransistors S_MT22 are driven by the fourth source line SL22. The secondmemory string is driven by the second bit line BL2.

Here, the first memory string and the second memory string may belong toone memory block or different memory blocks. When the first and secondmemory strings belong to one memory block, a first pipe transistor PTr1and a second pipe transistor PTr2 are driven by the same pipe gate. Whenthe first and second memory strings belong to different memory blocks,the first pipe transistor PTr1 and the second pipe transistor PTr2 aredriven by different pipe gates.

Referring to FIG. 1C, first to third memory strings according to anotherexemplary embodiment of the present invention may share bit lines BL1and BL2 or source lines SL1 to SL4.

Second source-side memory transistors S_MT12 of the first memory stringand third source-side memory transistors S_MT21 of the second memorystring share the second source line SL2. Fourth source-side memorytransistors S_MT22 of the second memory string and fifth source-sidememory transistors S_MT31 of the third memory string share the thirdsource line SL3.

Here, the first to third memory strings may be driven by different bitlines or some of the first to third memory strings may share a bit line.For example, the first and third memory strings may be driven by thefirst bit line BL1, and the second memory string may be driven by thesecond bit line BL2. In this case, first source-side memory transistorS_MT11 of the first memory string are driven by the first source lineSL1 and sixth source-side memory transistors S_MT32 of the third memorystring may be driven by the fourth source line SL4. As another example,the first to third memory strings are driven by first to third bitlines, respectively. In this case, the first source-side memorytransistors S_MT11 of the first memory string and the sixth source-sidememory transistors S_MT32 of the third memory string may share the firstsource line SL1.

Also, the first to third memory strings may belong to one memory blockor different memory blocks. When the first to third memory stringsbelong to one memory block, first to third pipe transistors PTr1 to PTr3are driven by the same pipe gate. When the first to third memory stringsbelong to different memory blocks, the first to third pipe transistorsPTr1 to PTr3 are driven by different pipe gates.

FIGS. 2A and 2B are circuit diagrams illustrating program operationsperformed on the memory string according to the exemplary embodiment ofthe present invention.

Referring to FIG. 2A, it will be described below that certain conditionsof voltages are applied to respective gates of various transistors whena program operation is performed by selecting a source-side memorytransistor included in the memory string according to the exemplaryembodiment of the present invention.

For example, when one of first source-side memory transistors S_MT1 isselected, a program voltage Vpgm is applied to a word line connected tothe selected first source-side memory transistor S_MT1 and a passvoltage Vpass is applied to the other word lines. A pass selectiontransistor PTr is turned on by applying the pass voltage Vpass to a gatethereof.

Also, a first source selection transistor SST1 is turned off by applyinga ground voltage (0 V) to a gate thereof, and an operating voltage Vccis applied to a first source line SL1. A drain selection transistor DSTis turned on by applying the operation voltage Vcc to a gate thereof,and a bit line BL is grounded. The non-selected second to k^(th) sourceselection transistors SST2 to SSTk are turned off or on, and second tok^(th) source lines SL2 to SLk are grounded.

Referring to FIG. 2B, it will be described below that certain conditionsof voltages are applied to respective gates of various transistors whena program operation is performed by selecting a drain-side memorytransistor included in the memory string according to the exemplaryembodiment of the present invention.

For example, when one of drain-side memory transistors D_MT is selected,a program voltage Vpgm is applied to a word line connected to theselected drain-side memory transistor D_MT and a pass voltage Vpass isapplied to the other word lines. A pass selection transistor PTr isturned on by applying the pass voltage Vpass to a gate thereof.

Also, one of first to k^(th) source selection transistors SST1 to SSTk,for example, a first source selection transistor SST1, is selected andturned off by applying a ground voltage (0 V) to a gate thereof, and anoperating voltage Vcc is applied to a first source line SL1 of the firstsource selection transistor SST1. A drain selection transistor DST isturned on by applying the operating voltage Vcc to a gate thereof, and abit line BL is grounded. The non-selected second to k^(th) sourceselection transistors SST2 to SSTk are turned off or on, and second tok^(th) source lines SL2 to SLk are grounded.

FIGS. 3A and 3B are circuit diagrams illustrating read operationsperformed on the memory string according to the exemplary embodiment ofthe present invention.

Referring to FIG. 3A, it will be described below that certain conditionsof voltages are applied to respective gates of various transistors whenthe read operation is performed by selecting a source-side memorytransistor included in the memory string according to the exemplaryembodiment of the present invention.

For example, when one of first source-side memory transistors S_MT1 isselected, a read voltage Vread is applied to a gate of the selectedfirst source-side memory transistor S_MT1 and a pass voltage Vpass isapplied to gates of the other first source-side memory transistorsS_MT1. Also, the pass voltage Vpass is applied to gates of drain-sidememory transistors D_MT. Here, the read voltage Vread is applied to readdata stored in a selected memory transistor, and has such a level thatit causes a programmed memory transistor to be turned off and an erasedmemory transistor to be turned on. Also, the pass voltage Vpass has sucha level that it causes a memory transistor to be turned on regardless ofa state of the memory transistor.

Also, a drain selection transistor DST and a selected first sourceselection transistor SST1 are turned on by applying an operating voltageVcc to gates thereof, a bit line BL is precharged to a high level (e.g.,the operating voltage Vcc), and a selected first source line SL1 ismaintained at a low level (e.g., a ground voltage). In this case, acurrent does not flow to the first source line SL1 when the selectedfirst source-side memory transistor S_MT1 is in a programmed state, andit flows to the first source line SL1 when the selected firstsource-side memory transistor S_MT1 is in an erased state. Thus, datastored in the selected first source-side memory transistor S_MT1 is readby sensing a level of a bit line BL.

The ground voltage (0 V) or the pass voltage Vpass is applied to gatesof the second to k^(th) source-side memory transistors S_MT2 to S_MTkthat are not selected, and the ground voltage (0 V) or the operatingvoltage Vcc is applied to gates of the second to k^(th) source selectiontransistors SST2 to SSTk that are not selected. Also, the second tok^(th) source lines SL2 to SLk that are not selected are maintained at ahigh level.

Referring to FIG. 3B, it will be described below that certain conditionsof voltages are applied to respective gates of various transistors whena read operation is performed by selecting a drain-side memorytransistor included in the memory string according to the exemplaryembodiment of the present invention.

For example, when one of drain-side memory transistors D_MT is selected,a read voltage Vread is applied to a gate of the selected drain-sidememory transistor D_MT and a pass voltage Vpass is applied to the otherdrain-side memory transistors D_MT.

One of first to k^(th) source lines SL1 to SLk, for example, a firstsource line SL1, is selected, an operating voltage Vcc is applied to agate of a first source selection transistor SST1 connected to the firstsource line SL1, and the pass voltage Vpass is applied to gates of thefirst source-side memory transistors S_MT1.

Also, a drain selection transistor DST is turned on by applying theoperating voltage Vcc to a gate thereof, a bit line BL is precharged toa high level (e.g., the operating voltage Vcc), and the first sourceline SL1 is maintained at a low level (e.g., the ground voltage). Inthis case, a current does not flow to the first source line SL1 when theselected drain-side memory transistor D_MT is in a programmed state, andit flows to the first source line SL1 when the selected drain-sidememory transistor D_MT is in an erased state. Thus, data stored in theselected drain-side memory transistor D_MT is read by sensing a level ofthe bit line BL.

The ground voltage (0 V) or the pass voltage Vpass is applied to gatesof the non-selected second to k^(th) source-side memory transistorsS_MT2 to S_MTk, and the ground voltage (0 V) or the operating voltageVcc is applied to gates of the non-selected second to k^(th) sourceselection transistors SST2 to SSTk. Also, the non-selected second tok^(th) source lines SL2 to SLk are maintained at a high level.

FIG. 4A is a cross-sectional view of a semiconductor device includingmemory strings according to a first exemplary embodiment of the presentinvention. In the present embodiment, it will be described below that afirst memory string and a second memory string are driven by differentbit lines and different source lines.

Referring to FIG. 4A, the semiconductor device according to the firstexemplary embodiment of the present invention includes a plurality ofchannel layers CH. Each of the channel layers CH includes a pipe channellayer P_CH, a drain-side channel layer D_CH, and first to k^(th) sourcechannel layers S_CH1 to S_CHk. Here, ‘k’ denotes an integer that isequal to or greater than ‘2’.

The pipe channel layer P_CH connects the drain-side channel layer D_CHand the first to k^(th) source channel layers S_CH1 to S_CHk. Forexample, the pipe channel layer P_CH connects the first source-sidechannel layer S_CH1, the drain-side channel layer D_CH, and the secondsource-side channel layer S_CH2 that are arranged in a first direction Iin the order listed. Here, the order in which the first source-sidechannel layer S_CH1, the drain-side channel layer D_CH, and the secondsource-side channel layer S_CH2 are arranged may be changed.

Also, the channel layers CH are arranged in the first direction I and asecond direction II crossing the first direction I. For example, thechannel layers CH may be arranged in the form of matrix or arranged in azigzag pattern to improve the degree of integration.

The semiconductor device according to the first exemplary embodiment ofthe present invention includes conductive layers 44 and insulatinglayers 45 that are alternately stacked on a substrate (SUB) 41. Theconductive layers 44 and the insulating layers 45 are patterned by slitsS, and the conductive layers 44 may be used as a gate. For example,among the conductive layers 44, the lowermost conductive layer 44 may bea pipe gate PG, at least one uppermost conductive layer 44 may beselection lines SSL and DSL, and the other conductive layers 44 may beword lines S_WL and D_WL. Here, the conductive layers 44 are stackedwhile surrounding the channel layers CH. For example, the pipe gate PGwraps the pipe channel layers P_CH. The source-side word lines S_WL andthe source selection lines SSL are stacked while surrounding thesource-side channel layers S_CH, and the drain-side word lines D_WL andthe drain selection lines DSL are stacked while surrounding thedrain-side channel layers D_CH.

The semiconductor device according to the first exemplary embodiment ofthe present invention further includes a memory layer 46 disposedbetween the channel layers CH and the word lines S_WL and D_WL. Thememory layer 46 may include a tunnel insulating layer, a data storagelayer, and a charge blocking layer. For example, the data storage layerincludes a trapping layer such as a nitride layer, a polysilicon layer,nano dots, a phase-change material layer, etc.

The semiconductor device according to the first exemplary embodiment ofthe present invention further includes source lines SL11, SL12, S21, andS22 connected to the source-side channel layers S_CH, and bit lines BL1and BL2 connected to the drain-side channel layers D_CH. The sourcelines SL11, SL12, S21, and S22 and the bit lines BL1, BL2 may extend ina direction in which they intersect each other.

In the structure described above, drain selection transistors DST areformed in regions in which the channel layers CH and the drain selectionlines DSL intersect one another, and source selection transistors SSTare formed in regions in which the channel layers CH and the sourceselection lines SSL intersect one another. Source-side memorytransistors S_MT are formed in regions in which the channel layers CHand the source-side word lines S_WL intersect one another, anddrain-side memory transistors D_MT are formed in regions in which thechannel layers CH and the drain-side word lines D_WL intersect oneanother.

Thus, a pipe transistor, a plurality of drain-side memory transistors,and at least one drain selection transistor that are connected in seriesto a drain terminal of the pipe transistor, and a plurality ofsource-side memory transistors and at least one source selectiontransistor that are connected in parallel to a source terminal of thepipe transistor, form one memory string together, and memory strings maybe arranged in the form of W.

As described above, the degree of memory integration may be improved byincreasing the number of memory transistors to be included in one memorystring and decreasing the number of slits S, compared to the relatedart.

FIG. 4B is a cross-sectional view of a semiconductor device to whichmemory strings according to a second exemplary embodiment of the presentinvention. In the present embodiment, it will be described below thatfirst to third memory strings share bit lines or source lines. Featuresof the semiconductor device of FIG. 4B that are the same as the previousembodiments will not be redundantly described here.

Referring to FIG. 4B, the semiconductor device according to the secondexemplary embodiment of the present invention includes a plurality ofchannel layers CH1 to CH3. For example, the first channel layer CH1includes a first pipe channel layer P_CH1, a first source-side channellayer S_CH11, a second source-side channel layer S_CH12, and a firstdrain-side channel layer D_CH1. The second and third channel layers CH2and CH3 may have the same structure as the first channel layer CH1. Thefirst to third channel layers CH1 to CH3 are sequentially arranged in afirst direction I.

The semiconductor device according to the second exemplary embodiment ofthe present invention further includes conductive layers 44 andinsulating layers 45 that are alternately stacked on a substrate 41. Theconductive layers 44 include a pipe gate PG, source and drain-side wordlines S_WL and D_WL, and source and drain selection lines SSL and DSL.

The semiconductor device according to the second exemplary embodiment ofthe present invention further includes a memory layer 46 disposedbetween the channel layers CH1 to CH3 and the word lines S_WL and D_WL.

The semiconductor device according to the second exemplary embodiment ofthe present invention further includes source lines SL1 to SL4 connectedto the source-side channel layers S_CH, and bit lines BL1 and BL2connected to the drain-side channel layers D_CH.

For example, the first and third channel layers CH1 and CH3 areconnected to the first bit line BL1, and the second channel layer CH2 isconnected to the second bit line BL2. In this case, the firstsource-side channel layer S_CH11 is connected to the first source lineSL1, the second source-side channel layer S_CH12 and a third source-sidechannel layer S_CH21 are connected to the second source line SL2, afourth source-side channel layer S_CH22 and a fifth source-side channellayer S_CH31 are connected to the third source line SL3, and a sixthsource-side channel layer S_CH32 is connected to the fourth source lineSL4.

As another example, the first to third channel layers CH1 to CH3 areconnected to the first to third bit lines BL1 to BL3, respectively (notshown). In this case, the first source-side channel layer S_CH11 and thesixth source-side channel layer S_CH32 share the first source line SL1,the second source-side channel layer S_CH12 and the third source-sidechannel layer S_CH21 share the second source line SL2, and the fourthsource-side channel layer S_CH22 and the fifth source-side channel layerS_CH31 share the third source line SL3.

In the structure described above, second source-side memory transistorsS_MT12 and third source-side memory transistors S_MT21 share thesource-side word lines S_WL, respectively. Also, fourth source-sidememory transistors S_MT22 and fifth source-side memory transistorsS_MT31 share the source-side word lines S_WL, respectively. Thus, thenumber of slits is reduced to decrease a cell area, compared to theembodiment described above with reference to FIG. 4A. Also, since theconductive layers 44 stacked increase in width, stacks may be preventedfrom being tilted during a fabrication process.

FIG. 4C is a cross-sectional view of a semiconductor device includingmemory strings according to a third exemplary embodiment of the presentinvention. In the present embodiment, it will be described below thatone string includes first to fourth source-side memory transistors.Features of the semiconductor device of FIG. 4C that are the same as theprevious embodiments will not be redundantly described here.

Referring to FIG. 4C, the semiconductor device according to the thirdexemplary embodiment of the present invention includes a plurality ofchannel layers CH1 and CH2. For example, each of the channel layers CH1and CH2 includes a pipe channel layer P_CH, first to fourth source-sidechannel layers S_CH, and a drain-side channel layer D_CH. For example, apipe channel layer P_CH1 connects a first source-side channel layerS_CH11, a second source-side channel layer S_CH12, a drain-side channellayer D_CH1, a third source-side channel layer S_CH13, and a fourthsource-side channel layer S_CH14 that are arranged in a first directionI in the order listed.

Here, the first channel layer CH1 and the second channel layer CH2 arearranged in a second direction II crossing the first direction I. Forexample, the first channel layer CH1 and the second channel layer CH2are arranged in a zigzag pattern such that the center axis thereof areoblique to the second direction II with an offset.

The semiconductor device according to the third exemplary embodiment ofthe present invention further includes conductive layers 44 andinsulating layers 45 that are alternately stacked on the substrate 41.The conductive layers 44 includes a pipe gate PG, source and drain-sideword lines S_WL and D_WL, and source and drain selection lines SSL andDSL.

The semiconductor device according to the third exemplary embodiment ofthe present invention further includes a memory layer 46 disposedbetween the channel layers CH1 and CH2 and the word lines S_WL and D_WL.

The semiconductor device according to the third exemplary embodiment ofthe present invention further includes source lines SL1 to SL4 connectedto the source-side channel layers S_CH, and bit lines BL1 and BL2connected to the drain-side channel layers D_CH. In the first channellayer CH1 and the second channel layer CH2, first source-side channellayers S_CH11 and S_CH21 share the first source line SL1, secondsource-side channel layers S_CH12 and S-CH22 share the second sourceline SL2, third source-side channel layers S_CH13 and S_CH23 share thethird source line SL3, and fourth source-side channel layers S_CH14 andS_CH24 share the fourth source line SL4.

In the structure described above, the first and second channel layersCH1 and CH2 arranged in the zigzag pattern share the first to fourthsource lines SL1 to SL4, thereby reducing the number of wires. Also,only one memory string is formed in one memory block in the firstdirection I, thereby reducing disturbances during a program operation.

FIG. 5 is a block diagram of the structure of a memory system 1000according to an exemplary embodiment of the present invention.

As illustrated in FIG. 5, the memory system 1000 according to thepresent embodiment includes a memory device 1200 and a controller 1100.

The memory device 1200 is used to store various types of data such astexts, graphics, software codes, etc. The memory device 1200 may be anon-volatile memory device and include memory strings as described abovewith reference to FIGS. 1A to 4C. Also, the memory device 1200 mayinclude a pass transistor, drain-side memory transistors connected inseries to a drain terminal of the pass transistor, and first to k^(th)source-side memory transistors connected in parallel to a sourceterminal of the pass transistor. Here, ‘k’ denotes an integer that isequal to or greater than ‘2’. The structure and method of fabricatingthe memory device 1200 are the same as described above and are notredundantly described here.

The controller 1100 is connected to a host and the memory device 1200,and may access the memory device 1200 in response to a request from thehost. For example, the controller 1100 may control read, write, erase,background operations, etc. of the memory device 1200.

The controller 1100 includes a random access memory (RAM) 1110, acentral processing unit (CPU) 1120, a host interface 1130, an errorcorrection code (ECC) circuit 1140, a memory interface 1150, etc.

Here, the RAM 1110 may be used as an operating memory of the CPU 1120, acache memory between the memory device 1200 and the host, a buffermemory between the memory device 1200 and the host, etc. The RAM 1110may be replaced with a static random access memory (SRAM), a read-onlymemory (ROM), etc.

The CPU 1120 may control overall operations of the controller 1100. Forexample, the CPU 1120 may operate a firmware such as a flash transitionlayer (FTL) stored in the RAM 1110.

The host interface 1130 may interface with the host. For example, thecontroller 1100 communicates with the host via at least one amongvarious interface protocols, such as a Universal Serial Bus (USB)protocol, a MultiMedia Card (MMC) protocol, a Peripheral ComponentInterconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, anAdvanced Technology Attachment (ATA) protocol, a serial-ATA protocol, aparallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol,an Enhanced Small Disk Interface (ESDI) protocol, an Integrated DriveElectronics (IDE) protocol, a private protocol, etc.

The ECC circuit 1140 may detect and correct an error in data read fromthe memory device 1200 using the ECC.

The memory interface 1150 may interface with the memory device 1200. Forexample, the memory interface 1150 includes a NAND or a NOR interface.

Alternatively, the controller 1100 may further include a buffer memory(not shown) for temporarily storing data. The buffer memory may be usedto temporarily store data transmitted to the outside via the hostinterface 1130 or data transmitted from the memory device 1200 via thememory interface 1150. The controller 1100 may further include a ROM forstoring code data used to interface with the host.

As described above, the memory system 1000 according to an exemplaryembodiment of the present invention includes the memory device 1200improved in cell current and interference characteristics, and may thushave improved characteristics.

FIG. 6 is a block diagram of a memory system 1000′ according to anotherexemplary embodiment of the present invention. The features of thememory system 1000′ of FIG. 6 that are the same as the previousembodiments will not be redundantly described here.

As illustrated in FIG. 6, the memory system 1000′ according to anotherexemplary embodiment of the present invention includes a memory device1200′ and a controller 1100. The controller 1100 includes a RAM 1110, aCPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface1150, etc.

The memory device 1200′ may be a non-volatile memory and include memorystrings as described above with reference to FIG. 1A to 4C. Also, thememory device 1200′ includes a pass transistor, drain-side memorytransistors connected in series to a drain terminal of the passtransistor, and first to k^(th) source-side memory transistors connectedin parallel to a source terminal of the pass transistor. Here, ‘k’denotes an integer that is equal to or greater than ‘2’. A structure ofand a method of fabricating the memory device 1200′ are the same asdescribed above and will not be described here in detail.

The memory device 1200′ may be a multi-chip package including aplurality of memory chips. The plurality of memory chips are dividedinto a plurality of groups. The plurality of groups may communicate withthe controller 1100 via first to k^(th) channels CH1 to CHk. Also,memory chips belonging to one of the plurality of groups may communicatewith the controller 1100 via a common channel. Alternatively, the memorysystem 1000′ may be modified such that one memory chip is connected toone channel.

As described above, the memory system 1000′ according to anotherexemplary embodiment of the present invention includes the memory device1000′ improved in cell current and interference characteristics and maythus have improved characteristics. In particular, when the memorydevice 1200′ is configured as a multi-chip package, the data storagecapacity and operating speed of the memory system 1000′ may be improved.

FIG. 7 is a block diagram illustrating a configuration of a computingsystem 2000 according to an exemplary embodiment of the presentinvention. The features of the computing system 2000 of FIG. 7 that arethe same as the previous embodiments will not be redundantly describedhere.

As illustrated in FIG. 7, the computing system 2000 according to anexemplary embodiment of the preset invention includes a memory device2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply2500, a system bus 2600, etc.

The memory device 2100 stores data provided from the user interface2400, data processed by the CPU 2200, etc. Also, the memory device 2100is electrically connected to the CPU 2200, the RAM 2300, the userinterface 2400, the power source 2500, etc. via the system bus 2600. Forexample, the memory device 2100 may be connected to the system bus 2600directly or via a controller (not shown). When the memory device 2100 isconnected directly to the system bus 2600, the functions of thecontroller may be performed using the CPU 2200, the RAM 2300, etc.

The memory device 2100 may be a non-volatile memory and include memorystrings as described above with reference to FIGS. 1A to 4C. The memorydevice 2100 further includes a pass transistor, drain-side memorytransistors connected in series to a drain terminal of the passtransistor, and first to k^(th) source-side memory transistors connectedin parallel to a source terminal of the pass transistor. Here, ‘k’denotes an integer that is equal to or greater than ‘2’. A structure ofand a method of fabricating the memory device 2100 are the same asdescribed above and will not be described here in detail.

Also, the memory device 2100 may be a multi-chip package including aplurality of memory chips as described above with reference to FIG. 6.

The computing system 2000 having the structure described above may be acomputer, a Ultra Mobile Personal Computer (UMPC), a workstation, anet-book, a Personal Digital Assistants (PDA), a portable computer, aweb tablet, a wireless phone, a mobile phone, a smart phone, an e-book,a Portable Multimedia Player (PMP), a portable game console, anavigation device, a black box, a digital camera, a 3-dimensional (3D)television, a digital audio recorder, a digital audio player, a digitalpicture recorder, a digital picture player, a digital video recorder, adigital video player, an apparatus capable of transmitting/receivinginformation in a wireless environment, one of various electronic devicesthat form a home, computer, a telematics network, a radio-frequencyidentification (RFID) device, etc.

As described above, the computing system 2000 according to an exemplaryembodiment of the present invention includes the memory device 2100improved in cell current and interference characteristics and may thushave improved characteristics.

FIG. 8 is a block diagram of a computing system 3000 according toanother exemplary embodiment of the present invention.

As illustrated in FIG. 8, the computing system 3000 according to anotherexemplary embodiment of the present invention includes a software layerincluding an operating system 3200, an application 3100, a file system3300, a translation layer 3400, etc. The computing system 3000 furtherincludes a hardware layer such as a memory device 3500.

The operating system 3200 may manage software and hardware resources,etc. of the computing system 3000, and is capable of controllingexecution of a program of a CPU (not shown). The application 3100, asvarious programs that may be performed by the computing system 3000, maybe a utility performed by the operating system 3200.

The file system 3300 means a logical structure used to manage data,files, etc. that are present in the computing system 3000, and systemizefiles or data to be stored in the memory device 3500 according to arule. The file system 3300 may be determined by the operating system3200 used in the computing system 3000. For example, when the operatingsystem 3200 is Windows by Microsoft, the file system 3300 may be a fileallocation table (FAT), an NT file system (NTFS), etc. When theoperating system 3200 is Unix/Linux, the file system 3300 may be anextended file system (EXT), a Unix file system (UFS), a journaling filesystem (JFS), etc.

Although the operating system 3200, the application 3100, and the filesystem 3300 are illustrated as separate blocks in FIG. 8, theapplication 3100 and the file system 3300 may be included in theoperating system 3200.

The translation layer 3400 translates an address into a form suitablefor the memory device 3500 in response to a request from the file system3300. For example, the translation layer 3400 translates a logic addressgenerated by the file system 3300 into a physical address of the memorydevice 3500. Here, mapping information between the logic address and thephysical address may be stored in the form of an address translationtable. For example, the translation layer 3400 may be a flashtranslation layer (FTL), a universal flash storage link layer (ULL),etc.

The memory device 3500 may be a non-volatile memory and include memorystrings as described above with reference to FIGS. 1A to 4C. Also, thememory device 3500 may further include a pass transistor, drain-sidememory transistors connected in series to a drain terminal of the passtransistor, and first to k^(th) source-side memory transistors connectedin parallel to a source terminal of the pass transistor. Here, ‘k’denotes an integer that is equal to or greater than ‘2’. The structureand method of fabricating the memory device 3500 are the same asdescribed above and are not described here in detail.

The computing system 3000 having the structure described above may bedivided into an operating system layer implemented in an upper-levelregion and a controller layer implemented in a lower-level region. Here,the application 3100, the operating system 3200, and the file system3300 may be included in the operating system layer, and driven by anoperating memory of the computing system 3000. The translation layer3400 may be included in the operating system layer or the controllerlayer.

As described above, the computing system 3000 according to anotherexemplary embodiment of the present invention includes the memory device3500 improved in cell current and interference characteristics and maythus have improved characteristics.

As described above, each of memory strings includes first to k^(th)source-side memory transistors connected in parallel to a sourceterminal of a pipe transistor. Also, each of the memory strings isconnected to a plurality of source lines. Thus, the integration degreeand cell current characteristics of a semiconductor device may beimproved. Also, the characteristics of the semiconductor device may beimproved by reducing interferences between memory cells.

In the drawings and specification, there have been disclosed typicalexemplary embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation. As for the scope of the invention, it is tobe set forth in the following claims. Therefore, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1-7. (canceled)
 8. A semiconductor device comprising: first and secondmemory strings each comprising: a pass transistor; drain-side memorycells connected in series to a drain terminal of the pass transistor;and first and second source-side memory groups connected in parallel toa source terminal of the pass transistor and each including a pluralityof source-side memory cells connected in series.
 9. The semiconductordevice of claim 8, further comprising: first source lines connected toand suitable for driving the first source-side memory groups,respectively; and second source lines connected to and suitable fordriving the second source-side memory groups, respectively.
 10. Thesemiconductor device of claim 8, further comprising: a first source linesuitable for driving the second source-side memory group of the firstmemory string and the first source-side memory group of the secondmemory string; and second source lines suitable for driving the firstsource-side memory group of the first memory string and the secondsource-side memory group of the second memory string, respectively. 11.The semiconductor device of claim 8, further comprising: a first bitline suitable for driving the drain-side memory cells of the firstmemory string; and a second bit line suitable for driving the drain-sidememory cells of the second memory string.
 12. The semiconductor deviceof claim 8, further comprising a third memory string configured as thesame as the first and second memory strings, wherein the source linecomprises: a first source line suitable for driving the secondsource-side memory group of the first memory string and the firstsource-side memory group of the second memory string; a second sourceline suitable for driving the second source-side memory group of thesecond memory string and a first source-side memory group of the thirdmemory string; and third source lines suitable for driving the firstsource-side memory group of the first memory string and a secondsource-side memory group of the third memory string, respectively. 13.The semiconductor device of claim 12, further comprising: a first bitline suitable for driving drain-side memory cells of the first and thirdmemory strings; and a second bit line suitable for driving thedrain-side memory cells of the second memory string.
 14. A semiconductordevice comprising: a first channel layer comprising: a first pipechannel layer; and a first source-side channel layer, a first drain-sidechannel layer, and a second source-side channel layer connected to thefirst pipe channel layer, and arranged in a first direction; firstsource-side gates stacked and surrounding the first source-side channellayer; second source-side gates stacked and surrounding the secondsource-side channel layer; and first drain-side gates stacked andsurrounding the first drain-side channel layer, wherein the firstsource-side gates, the second source-side gates, and the firstdrain-side gates are separated from one another.
 15. The semiconductordevice of claim 14, further comprising: a second channel layer arrangedadjacent to the first channel layer in the first direction, andincluding a second pipe channel layer, and a third source-side channellayer, a second drain-side channel layer, and a fourth source-sidechannel layer connected to the second pipe channel layer and arranged inthe first direction.
 16. The semiconductor device of claim 15, furthercomprising: first to fourth source lines connected to the first tofourth source-side channel layers, respectively; and first and secondbit lines connected to the first and second drain-side channel layer,respectively.
 17. The semiconductor device of claim 15, wherein thesecond source-side channel layer and the third source-side channel layerare connected to a same source line, and the first drain-side channellayer and the second drain-side channel layer are connected to differentbit lines.
 18. The semiconductor device of claim 14, further comprising:a second channel layer arranged adjacent to the first channel layer in asecond direction crossing the first direction, and including a secondpipe channel layer, and a third source-side channel layer, a seconddrain-side channel layer, and a fourth source-side channel layerconnected to the second pipe channel layer and arranged in the firstdirection.
 19. The semiconductor device of claim 18, further comprising:a first source line connected to the first and third source-side channellayers; a second source lines connected to the second and fourthsource-side channel layers; and first and second bit lines connected tothe first and second drain-side channel layers, respectively, whereinthe first channel layer and the second channel layer are arranged in thesecond direction to have a center axis oblique to the second direction.20. The semiconductor device of claim 14, wherein the first channellayer further comprises: a third source-side channel layer connected tothe first pipe channel layer and disposed between the first source-sidechannel layer and the first drain-side channel layer; and a fourthsource-side channel layer connected to the first pipe channel layer anddisposed between the second source-side channel layer and the firstdrain-side channel layer, wherein the semiconductor device includesmemory blocks each having the first channel layer in the firstdirection.